发布时间 : 星期四 文章EDA课程设计整点报时电路源程序及测试平台更新完毕开始阅读
源程序：
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity zdbs is
port(clk,rst:in std_logic; clk_1024:in std_logic; spk:out std_logic;
h1,h2,s1,s2:out std_logic_vector(3 downto 0); m1,m2:buffer std_logic_vector(3 downto 0)); end zdbs;
architecture rtl of zdbs is
signal h,s:integer range 0 to 59; signal aleart:std_logic; begin
process(clk)
variable temp1:std_logic_vector(3 downto 0):=\ variable temp2:std_logic_vector(3 downto 0):=\ variable temp3:std_logic_vector(3 downto 0):=\ variable temp4:std_logic_vector(3 downto 0):=\ variable temp5:std_logic_vector(3 downto 0):=\ variable temp6:std_logic_vector(3 downto 0):=\ begin
if rst='1' then temp1:=\ temp2:=\ temp3:=\
temp4:=\ temp5:=\ temp6:=\ else
if(clk'event and clk='1')then temp6:=temp6+1;
if(temp6=10)then
temp6:=(others=>'0'); temp5:=temp5+1;
if (temp5=6)then
temp5:=(others=>'0'); temp4:=temp4+1; if(temp4=10)then
temp4:=(others=>'0');
temp3:=temp3+1; if(temp3=6)then
temp3:=(others=>'0'); temp2:=temp2+1; if(temp2=10)then
temp2:=(others=>'0'); temp1:=temp1+1;
end if;
if((temp1=2)and(temp2=4))then temp1:=(others=>'0'); temp2:=(others=>'0');
end if; end if; end if; end if; end if; end if; end if;
h<=10*conv_integer(temp1)+conv_integer(temp2); s<=10*conv_integer(temp5)+conv_integer(temp6); h1<=temp1; h2<=temp2; m1<=temp3; m2<=temp4; s1<=temp5; s2<=temp6; end process;
process(m1,m2,h,s) begin
if((m1=0)and(m2=0)and(s aleart<='0'; end if; end process; process(aleart,clk,clk_1024) begin if(aleart='1')then spk<=clk and clk_1024; else spk<='Z'; end if; end process; end rtl; 测试平台 library ieee; use ieee.std_logic_1164.all; entity test is end test; architecture behaviour of test is signal sig_clk : std_logic :='0' ; signal sig_clk_1024 : std_logic :='1'; signal sig_rst : std_logic :='0'; signal sig_h1 : std_logic_vector(3 downto 0); signal sig_h2 : std_logic_vector(3 downto 0); signal sig_m1 : std_logic_vector(3 downto 0); signal sig_m2 : std_logic_vector(3 downto 0); signal sig_s1 : std_logic_vector(3 downto 0); signal sig_s2 : std_logic_vector(3 downto 0); signal sig_spk : std_logic; constant period: time :=5 ns; component zdbs port ( clk,clk_1024,rst : in std_logic; m1,m2 : buffer std_logic_vector(3 downto 0); spk : out std_logic; h1,h2,s1,s2 : out std_logic_vector(3 downto 0) ); end component; begin -- instance u_zdbs : zdbs port map ( clk => sig_clk, clk_1024 => sig_clk_1024, rst => sig_rst, h1 => sig_h1, h2 => sig_h2, m1 => sig_m1, m2 => sig_m2, spk => sig_spk, s1 => sig_s1, s2 => sig_s2 ); process begin sig_clk <='0';wait for period; sig_clk <='1'; wait for period; end process; sig_rst <= '0'; sig_clk_1024 <='1','0' after 10 ns, '1' after 20 ns; end behaviour;