基于VerilogHDL语言的串口设计说?- 百度文库

ʱ : 基于VerilogHDL语言的串口设计说?- 百度文库ϿʼĶ

.

endmodule

Ϊ˲շǷдTest Bench

`timescale 1ns/1ns module trsb;

reg clk,rst,en; reg [7:0]TxD_data; reg [2:0]Wsec;

wire TxD,TxD_busy,rcven; wire [7:0]RxD_data; trans trsb(.clk(clk), .rst(rst), .en(en), .TxD(TxD), .Wsec(Wsec),

.TxD_busy(TxD_busy), .TxD_data(TxD_data), .rcven(rcven),

.RxD_data(RxD_data), .RxD(TxD) ); initial begin en = 0;

TxD_data = 0; rst = 1; #1 Wsec=2; #54 rst=0; #70 rst=1;

#10 TxD_data = 8'b11011001; #10 en = 1'b1;

#1250000 en = 1'b1;

end initial begin

#3790000 TxD_data = 8'b01011010; #10 en = 1'b1;

#2750000 en = 1'b0;

#1290000 TxD_data = 8'b101001010; #10 en = 1'b1;

#2750000 en = 1'b0;

. . .

.

end

initial begin clk = 1; while (1)

#10 clk = ~clk; end

endmodule

FPGAʵִнӿ RS232(1) 2008-12-17 11:38

нӿ(RS-232)

нӿFPGAPCһּ򵥷ʽĿչʾʹFPGARS-232շ

Ŀ5

1. 2. 3. 4. 5.

RS232 βҪIJ ģ ģ Ӧʵ

RS-232ӿ

Ϊ׼豸ļ12RS-232ڡ

RS-232:

? ? ?

ʹ9\ͷ(ʽʹ25\ͷ).

ȫ˫˫ͨѶ(Ҳ˵ڽݵͬʱ). ֵ֧ĴΪ10KBytes/s.

DB-9ͷ

Ѿļֲͷ

. . .

.

һ9ţҪ3:

? ? ?

2: RxD (). 3: TxD (). 5: GND ().

ʹ3£ͿԷͺͽ.

ͨѶ

ÿһλķʽ䣻ÿһݡڼͨҪλݣڷ֮ǰȡлͨ8λΪ1ġ ȷЧλЧλ

첽ͨѶ

RS-232ʹ첽ͨѶЭ顣Ҳ˵ݵĴûʱźšն˱ijַʽʹ֮ͬ RS-232˵:

1. µԼôдIJٶȡʽȣ 2. ûݴʱ򣬷ͶϷ\

3. ÿһֽ֮ǰͶȷһ\ʾѾʼն˱

֪ݵˡ

4. ʼԼٶȺ͸ʽ䣬Խն˿֮ͬ 5. ÿδһֽ֮󣬶һֹͣλ(\

0x55δ:

0x55ĶƱʾΪ01010101

ȷ͵ЧλԷ: 1-0-1-0-1-0-1-0. һ :

Ϊ0xC4ܿ? ͼкѿݣҲ˵֪ʶڽնжôҪ

ݴԶ?

. . .

.

ݵĴٶòģ༴ÿӴλ1000رʾÿӴ100ص, ˵ÿλ1롣

ʲģһı׼ϣ123456صRS-232ӿڣԲܲˣDzеġõĴдֵ¼֣

? ? ? ?

1200 .

9600 . 38400 .

115200 (ͨʹõٶ).

115200 شٶ, ÿλݳ (1/115200) = 8.7s. 8λ, 8 x 8.7s = 69sÿֽڵĴҪġʼλֹͣ͡λ,ʵҪ10 x 8.7s = 87sʱ䡣Чݴֻܴﵽ 11.5KBytesÿ롣

115200 شٶ,һЩʹ˲õоƬļҪһֹͣλ(1.52λݵij)ʹٶȽԼ10.5KBytesÿ

ϵźʹѹĻ:

? ?

\ -10V ĵѹʾ( -5V -15V֮ĵѹ). \ +10V ĵѹʾ( 5V 15V֮ĵѹ).

ûݴĵϵĵѹӦΪ-10V-5-10֮ijѹ

FPGAʵִнӿ RS232(2) 2008-12-17 11:39

ʷ

ʹôӵٶ115200أIJҲɴ˲

FPGAͨԶ115200HzʱƵϣڽı׼˵RS-232̫ˣζҪһϸߵʱƵӽ115200Hzʱźš 1.8432MHzʱӲ

ͨRS-232оƬʹ1.8432MHzʱӣΪʱӺײ׼IJʣǼѾӵһʱԴ

ֻҪ 1.8432MHz 16Ƶɵõ 115200Hzʱӣ෽㰡 reg [3:0] BaudDivCnt;

always (posedge clk) BaudDivCnt <= BaudDivCnt + 1; wire BaudTick = (BaudDivCnt==15);

\ÿ16ʱҪλһΣӶ1.8432MHzʱӵ

. . .

ϵͬͷxxxxx#qq.com(#滻Ϊ@)