发布时间 : 星期日 文章FPGA底层代码，正弦波，方波，三角波，锯齿波 - 文本资料更新完毕开始阅读
一． 频率控制模块 代码 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY FREQUENCY IS
PORT ( CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(4 DOWNTO 0);--设置A的初值 FOUT : OUT STD_LOGIC ); END;
ARCHITECTURE one OF FREQUENCY IS
SIGNAL FULL : STD_LOGIC; BEGIN
P_REG: PROCESS(CLK)
VARIABLE CNT1 : STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN
IF CLK'EVENT AND CLK = '1' THEN IF CNT1 = \
CNT1 := A; --当CNT1计数计满时，输入数据D被同步预置给计数器 CNT1
FULL <= '1'; --同时使溢出标志信号FULL输出为高电平 ELSE CNT1 := CNT1 + 1; --否则继续作加1计数
FULL <= '0'; --且输出溢出标志信号FULL为低电平 END IF; END IF;
END PROCESS P_REG P_DIV: PROCESS(FULL)
VARIABLE CNT2 : STD_LOGIC; BEGIN
IF FULL'EVENT AND FULL = '1' THEN
CNT2 := NOT CNT2; --如果溢出标志信号FULL为高电平，D触发器输出取反 IF CNT2 = '1' THEN FOUT <= '1'; ELSE FOUT <= '0'; END IF; END IF;
END PROCESS P_DIV END;
九．按键选择模块 代码
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY BUTTON IS
PORT ( d : IN STD_LOGIC_VECTOR(2 DOWNTO 0) a,b,c : OUT STD_LOGIC ) END; ARCHITECTURE ONE OF BUTTON IS BEGIN
PROCESS( d ) BEGIN
CASE d IS
WHEN \
WHEN OTHERS => a <= d(0);--dlt b <= d(1);--sqr c <= d(2);--sin END CASE; END PROCESS; END;
三角波信号产生模块 代码
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity delta is
port ( clk : in std_logic clr : in std_logic;
q : out std_logic_vector(7 downto 0) ) end delta;
architecture one of delta is begin
process( clk,clr)
variable num : std_logic_vector(7 downto 0); variable ff : std_logic; begin
if clr = '0' then
num := \
else if clk'event and clk = '1' then--时钟信号有上升沿时有效 if ff = '0' then
if num = \ ff :='1'; else
num := num + 8;
end if;--以上，ff=0时，上升，直至num加到11111000时，使ff=1 else
if num = \ num := \ ff := '0'; else
num := num -8;--以上，ff=1时，下降，直至num减到00000111时，使ff=0 end if; end if; end if; end if;
q <= num;--每一次脉冲，将num的值给q以输出 end process end;
四．方波信号产生模块 代码 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity aquare is
port ( clk : in std_logic clr : in std_logic;
q : out std_logic_vector(7 downto 0) ) end aquare;
architecture one of aquare is signal ff:bit; begin
p1:process( clk,clr)
variable num : std_logic_vector(5 downto 0); begin
if clr = '0' then ff <= '0';
else if clk'event and clk = '1' then--当时钟脉冲有一个上升沿 if num < 31 then num := num+1; else
num := \
ff <= not ff;--num每次加1，加32次ff取反1次 end if; end if; end if;
end process p1; p2: process( clk,ff) begin
if clk'event and clk = '1' then if ff = '1' then
q <= \时输出高电平 else
q <= \时输出低电平 end if; end if; end process p2; end;