发布时间 : 星期日 文章基于FPGA的计时器的设计毕业设计更新完毕开始阅读
图A1 RTL视图
附录B 计费模块的Verilog HDL语言描述
module MONEY( iclk, iclk_50M, irst, imoney, iset, icall, omoney, otime, set, oclk_counter, oLED_warning, oLED_phoneing );
input iclk;
input iclk_50M; input irst; input icall;
input [7:0] imoney; input [1:0] iset;
output [5:0]oclk_counter; output [6:0]omoney; output [6:0]otime; output [1:0] set;
output oLED_phoneing; output oLED_warning;
reg start ; reg [1:0]set_r; reg [5:0]clk_counter_r; reg [6:0]omoney_r; reg [6:0]otime_r; reg LED_phoneing_r; reg LED_warning_r;
// 通话开始，结束变量 // 什么类型的通话 // 秒计数器 // 剩余余额
// 通话多少分钟计数器 // 通话灯
// 余额不足警告灯
reg STOP; // 余额不足一分钟后停止
assign omoney = omoney_r; assign otime = otime_r; assign set = set_r;
assign oclk_counter = clk_counter_r; assign oLED_phoneing = LED_phoneing_r; assign oLED_warning = LED_warning_r;
always@(posedge iclk_50M,negedge irst) begin if (!irst) start <= 0; else if(STOP) start <= 0; else if(icall) start <= 1; else start <= 0; end
//每60秒一分钟
always@(posedge iclk,negedge irst) begin if (!irst) clk_counter_r <= 0; else if(start) begin if(clk_counter_r <6'd59) clk_counter_r <= clk_counter_r + 1; else clk_counter_r <= 0; end end
//通话计时
always@(posedge iclk,negedge irst) begin if (!irst) otime_r <= 0; else if(clk_counter_r == 6'd59) otime_r <= otime_r + 1; end
//先扣费 ， 后接通电话
always@(posedge iclk,negedge irst) begin if (!irst) omoney_r <= 0; else if (!icall) begin if(imoney > 99) omoney_r <= 99; else omoney_r <= imoney; set_r <= iset; end else begin if((otime_r == 0)&&(clk_counter_r == 0)) case (set_r) 2'b01 : omoney_r <= omoney_r - 2; 2'b10 : omoney_r <= omoney_r - 7; 2'b11 : omoney_r <= omoney_r - 12; endcase if(!LED_warning_r) begin if(clk_counter_r == 6'd59) case (set_r) 2'b01 : omoney_r <= omoney_r - 2; 2'b10 : omoney_r <= omoney_r - 7; 2'b11 : omoney_r <= omoney_r - 12; endcase end else if(STOP == 1) set_r <= 0; end end
//通话提示
always@(posedge iclk,negedge irst)
begin if (!irst) LED_phoneing_r <= 0; else LED_phoneing_r <= start; end
//余额不足提示
always@(posedge iclk,negedge irst) begin if (!irst) LED_warning_r <= 0; else if(STOP == 1) LED_warning_r <= 0; else case (set_r) 2'b01 : if(omoney_r <3) LED_warning_r <= 1; else LED_warning_r <= 0; 2'b10 : if(omoney_r <6) LED_warning_r <= 1; else LED_warning_r <= 0; 2'b11 : if(omoney_r <12) LED_warning_r <= 1; else LED_warning_r <= 0; endcase end
always@(posedge iclk,negedge irst) begin if (!irst) STOP <= 0; else if((clk_counter_r == 6'd59)&&(LED_warning_r == 1)) STOP <= 1; end