发布时间 : 星期一 文章基于FPGA的千兆以太网设计 - 图文更新完毕开始阅读
摘 要
摘 要
随着信息技术的快速发展，以太网嵌入式设备的应用越来越广泛。为了让以太网各设备之间能公平有效地共享通信媒介，对以太网MAC层数据处理系统的研究显得尤为重要。
为此，本文首先分析了以太网及其相关协议的基本内涵，解剖了以太网MAC层通信机制、帧的特性与格式、PHY接口协议、ARP协议以及I2C协议。同时通过对FPGA芯片的了解，确定了基于88E1111芯片和XC3S400FPGA芯片相结合的系统设计方案，支持1000Base-T标准以太网的接入，完成了系统的硬件电路设计。系统设计中，88E1111完成PHY层数据的处理，FPGA则完成MAC层数据的处理，主要包含接收MAC数据帧的校验和解封、待发送数据帧的封装、MAC地址滤波、IP数据包的提取、ARP地址映射等，是系统的核心。在FPGA设计中，遵循自上而下的设计思想，对顶层模块以及PHY接口、MAC核心处理、用户配置、用户数据各功能子模块依次进行设计。
关键词：以太网 MAC层 FPGA
ABSTRACT
ABSTRACT
With the rapid development of IT,the embedded devices of accessing to Ethernet are used more and more widely.In order to make each device enjoy a fair and effective shared communications medium, it is particularly important to research the data processing system of the Ethernet MAC layer.
To this end,it is firstly done to analyze the basic connotation of Ethernet and the related agreements,and to dissect the communication mechanisms of the Ethernet MAC layer,the characteristics and format of the frame,the PHY interface protocol,the ARP protocol,I2C protocol in the paper.According to the characteristics and working principle of the FPGA chip ,the system design, which supports the accessing of the 1000Base-T Ethernet,is determined based on the combination of the 88E1111 PHY chip and XC3S400-4fg456C FPGA chip of Xilinx.Then the hardware circuit design is accomplished by the Cadence development tool.In this system, 88E1111 and FPGA respectively completes the data processing of PHY layer and the data processing of the MAC layer,which mainly consists of the calibration and dearchive of the receiving data frames, the encapsulation of the data frames,the MAC address filtering, the extraction of the IP packet,The ARP address mapping,and so on. So FPGA is the core of the system. Following the top-down design conception,the design of FPGA successively includes the top-level module,and the submodule of the PHY interface,the MAC core processing,the user configuration,the user data interface.
Keywords: Ethernet the MAC layer FPGA
目 录 i
目 录
第一章 绪论 ........................................................................................................ 1
1.1研究背景及意义 ..................................................................................... 1 1.2国内外研究现状 ..................................................................................... 2 1.3论文内容和论文组织结构安排 ............................................................. 3 第二章 千兆以太网理论基础 ............................................................................ 5
2.1千兆以太网标准 ..................................................................................... 5 2.2介质访问控制（MAC） ........................................................................ 7
2.2.1半双工MAC .............................................................................. 7 2.2.2全双工MAC .............................................................................. 9 2.3介质无关接口（MII） ......................................................................... 10
2.3.1GMII接口信号定义 ................................................................. 11 2.3.2GMII接口时序特性 ................................................................. 14 2.3.3GMII的管理MDIO接口 ......................................................... 15 2.4物理层技术 ........................................................................................... 17 2.5TCP/IP协议栈 ....................................................................................... 18 第三章 以太网数据传输硬件设计实现 .......................................................... 21
3.1系统方案设计 ....................................................................................... 21
3.1.1设计思想 ................................................................................... 21 3.1.2系统功能 ................................................................................... 21 3.1.3系统总体结构设计 ................................................................... 22 3.2芯片的选取 ........................................................................................... 23
3.2.1物理层芯片选择 ....................................................................... 23 3.2.2FPGA主芯片选择 .................................................................... 25 3.3硬件电路设计 ....................................................................................... 26
3.3.1以太网变换电路设计 ............................................................... 26
第四章 FPGA软件设计与仿真 ...................................................................... 33
ii 目 录
4.1FPGA软件开发简介 ............................................................................ 33 4.2系统顶层模块设计 .............................................................................. 34 4.3PHY接口模块设计 .............................................................................. 38
4.3.1设计思想 .................................................................................. 38 4.3.2相关算法 .................................................................................. 39 4.3.3功能仿真 .................................................................................. 40 4.4MAC核心处理模块设计 ..................................................................... 41 4.5实验测试与结果 .................................................................................. 42
4.5.1硬件测试平台准备 .................................................................. 42 4.5.2软件测试平台准备 .................................................................. 43 4.5.3系统测试与结果分析 .............................................................. 45
第五章 结论与展望 ......................................................................................... 49 致谢.................................................................................................................... 51 参考文献 ........................................................................................................... 53