发布时间 : 星期五 文章数字钟verilog更新完毕开始阅读
多功能数字钟verilog HDL设计
reg [3:0] hour_set1,hour_set0; //存放设置的小时 reg [3:0] minute_set1,minute_set0; //存放设置的分
reg [2:0] disp_drive; //设置闹钟时间时，数码管显示的动态位选择 //闹钟一直工作（设置的闹钟时间与当前时间比较） always begin
if((hour_set1 == hour1)&&(hour_set0 == hour0) &&(minute_set1
==minute1)&&(minute_set0==minute0)&&(control_alarm==1)) alarm <= 1'b1; //相等，闹钟响 else if(control_alarm==0) alarm <= 1'b0; //不相等，输出1 end
//闹钟设置中，按SW1一次，将移位一次，显示当前设置位 always @(posedge SW1) begin
if(EN == 1'b1) begin
if(disp_drive != 3'b101)
disp_drive <= disp_drive + 3'b1; else
disp_drive <= 3'b000; end end
//当前位的闹钟数字设置，按SW2一次，数字增加1 always @(posedge SW2) begin
case(disp_drive)
3'b000: begin //000时，设置小时的高位 if(hour_set1 < 4'b0010) hour_set1 <= hour_set1 + 4'b1; else hour_set1 <= 4'b0; end 3'b001: begin //001时，小时低位 if((hour_set1 < 4'b0010)&&(hour_set0 < 4'b1001)) hour_set0 <= hour_set0 + 4'b1; else if((hour_set1==4'b0010)&&(hour_set0 < 4'b0100)) hour_set0 <= hour_set0 + 4'b1; else hour_set0 <= 4'b0; end
3'b010: begin //010时，分钟高位 if(minute_set1 < 4'b0101) minute_set1 <= minute_set1 + 4'b1;
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多功能数字钟verilog HDL设计
else minute_set1 <= 4'b0; end
3'b011: begin //011时，分钟低位 if(minute_set0 < 4'b1001) minute_set0 <= minute_set0 + 4'b1; else minute_set0 <= 4'b0; end endcase end
//闪烁显示
always @(posedge clk_200hz) //设置时闪烁频率 begin
case(disp_drive)
3'b000: alarmclock_disp_select <= 6'b1000; 3'b001: alarmclock_disp_select <= 6'b0100; 3'b010: alarmclock_disp_select <= 6'b0010; 3'b011: alarmclock_disp_select <= 6'b0001; default: alarmclock_disp_select <= 6'b0000; endcase end endmodule
6.时间设置模块
module timeset( TimeSet_EN, SW1,SW2,disp_drive， hour1,hour0, minute1,minute0, hour_set1,hour_set0,minute_set1,minute_set0 ); input TimeSet_EN; input SW1,SW2;
input [3:0] hour1,hour0;
input [3:0] minute1,minute0; output [3:0] hour_set1,hour_set0; output [3:0] minute_set1,minute_set0; output [2:0] disp_drive;
reg [3:0] hour_set1,hour_set0; reg [3:0] minute_set1,minute_set0; reg [2:0] disp_drive; //初始化 initial begin
hour_set1 <= hour1;
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多功能数字钟verilog HDL设计
hour_set0 <= hour0; minute_set1 <= minute1; minute_set0 <= minute0; end
always @(posedge SW1) //手动设置使能 begin
if(TimeSet_EN == 1'b1) begin
if(disp_drive < 3'b101)
disp_drive <= disp_drive + 3'b1; else
disp_drive <= 3'b0; end end
always @(posedge SW2) begin
case(disp_drive)
3'b000: begin //小时的高位
if(hour_set1 < 4'b0010)
hour_set1 <= hour_set1 + 4'b1; else
hour_set1 <= 4'b0; end
3'b001: begin //小时的低位 if(hour_set0 < 4'b1001) hour_set0 <= hour_set0 + 4'b1; else hour_set0 <= 4'b0; end
3'b010: begin //分的高位 if(minute_set1 < 4'b0101) minute_set1 <= minute_set1 + 4'b1; else minute_set1 <= 4'b0; end
3'b011: begin //分的低位
if(minute_set0 < 4'b1001)
minute_set0 <= minute_set0 + 4'b1; else
minute_set0 <= 4'b0; end default:begin end endcase
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多功能数字钟verilog HDL设计
end
endmodule 7.报时模块
Module Radio(alarm_radio,minute1,minute0,second1,second0,
minute,second, f1khz,f500hz);
input f1khz,f500hz;
input[3:0]minute1,minute0,second1,second0; input[7:0]minute,second;
output alarm_radio; //拼接之后时间 reg alarm_radio; //报时输出信号
always@(minute1 or minute0 or second1 or second0) begin
reg [7:0] minute,second;
{minute[7:0]}={minute1[3:0],minute0[3:0]}; //分拼接 {second[7:0]}={second1[3:0],second0[3:0]}; //秒拼接 end
always@(minute or second)
if(minute==8'h59) //59分钟时
case(second) //秒为50、52、54、56、58低音报时 8'h50, 8'h52, 8'h54, 8'h56,
8'h58:alarm_radio<=f500hz; default:alarm_radio<=1'b0; endcase
else if(minute==8'h00&&second==8'h00) //00分00秒高音报时 alarm_radio<=f1khz; else
alarm_radio<=1'b0; endmodule 8.控制显示模块
module disp_data_mux(Time_EN,TimeSet_EN,Stopwatch_EN, time_disp_select，Alarmclock_EN, alarmclock_disp_select, hour1,hour0,minute1,minute0,second1,second0, disp_select,disp_data,Data); input Time_EN,TimeSet_EN,Stopwatch_EN; input [5:0] time_disp_select; input Alarmclock_EN;
input [5:0] alarmclock_disp_select;
input [3:0] hour1,hour0,minute1,minute0,second1,second0;
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