发布时间 : 星期三 文章毕业论文 - 基于51单片机和NRF24L01的无线温度监控 - 图文更新完毕开始阅读
接收机
八、程序清单
发射端程序： #include
#define uchar unsigned char
没有天生的聪明 只有不懈的努力
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#define uint unsigned int
// Define interface to nRF24L01
// SPI(nRF24L01) commands
#define READ_REG 0x00 // Define read command to register #define WRITE_REG 0x20 // Define write command to register #define RD_RX_PLOAD 0x61 // Define RX payload register address #define WR_TX_PLOAD 0xA0 // Define TX payload register address #define FLUSH_TX 0xE1 // Define flush TX register command #define FLUSH_RX 0xE2 // Define flush RX register command
#define REUSE_TX_PL 0xE3 // Define reuse TX payload register command
#define NOP 0xFF // Define No Operation, might be used to read status register
// SPI(nRF24L01) registers(addresses)
#define CONFIG 0x00 // 'Config' register address
#define EN_AA 0x01 // 'Enable Auto Acknowledgment' register address #define EN_RXADDR 0x02 // 'Enabled RX addresses' register address #define SETUP_AW 0x03 // 'Setup address width' register address #define SETUP_RETR 0x04 // 'Setup Auto. Retrans' register address #define RF_CH 0x05 // 'RF channel' register address #define RF_SETUP 0x06 // 'RF setup' register address #define STATUS 0x07 // 'Status' register address
#define OBSERVE_TX 0x08 // 'Observe TX' register address #define CD 0x09 // 'Carrier Detect' register address
#define RX_ADDR_P0 0x0A // 'RX address pipe0' register address #define RX_ADDR_P1 0x0B // 'RX address pipe1' register address #define RX_ADDR_P2 0x0C // 'RX address pipe2' register address #define RX_ADDR_P3 0x0D // 'RX address pipe3' register address #define RX_ADDR_P4 0x0E // 'RX address pipe4' register address #define RX_ADDR_P5 0x0F // 'RX address pipe5' register address #define TX_ADDR 0x10 // 'TX address' register address
#define RX_PW_P0 0x11 // 'RX payload width, pipe0' register address #define RX_PW_P1 0x12 // 'RX payload width, pipe1' register address #define RX_PW_P2 0x13 // 'RX payload width, pipe2' register address #define RX_PW_P3 0x14 // 'RX payload width, pipe3' register address #define RX_PW_P4 0x15 // 'RX payload width, pipe4' register address #define RX_PW_P5 0x16 // 'RX payload width, pipe5' register address #define FIFO_STATUS 0x17 // 'FIFO Status Register' register address
#define TX_ADR_WIDTH 5 #define RX_ADR_WIDTH 5 #define TX_PLOAD_WIDTH 4 #define TX_PLOAD_WIDTH 4
float f_temp; uint temp;
uchar TX_ADDRESS[5]={0x34,0x43,0x19,0x91,0x09}; sbit CE=P2^7; sbit CSN=P2^2; sbit MOSI=P2^3; sbit MISO=P2^5; sbit SCK=P2^6; sbit IRQ=P2^4; sbit ds=P3^7; sbit led0=P1^0; uchar bdata sta;
sbit RX_DR= sta^6; sbit TX_DS= sta^5; sbit MAX_RT= sta^4;
void init_io(void) {
CE = 0; // 待机 CSN = 1; // SPI禁止 SCK = 0; // SPI时钟置低 IRQ = 1; // 中断复位 }
uchar SPI_RW(uchar byte) { uchar i; for(i=0;i<8;i++) { MOSI=(byte&0x80); byte=(byte<<1); SCK=1; byte|=MISO; SCK=0; } return(byte); }
uchar SPI_RW_reg(uchar reg,uchar value) { uchar status; CSN=0; status=SPI_RW(reg); SPI_RW(value);
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CSN=1; return(status); }
uchar SPI_read(uchar reg) { uchar reg_val; CSN=0; SPI_RW(reg); reg_val=SPI_RW(0); CSN=1; return(reg_val); }
uchar SPI_read_pload(uchar reg,uchar *pBuf,uchar bytes) { uchar status,i; CSN=0; status=SPI_RW(reg); for(i=0;i uchar SPI_write_pload(uchar reg,uchar *pBuf,uchar bytes) { uchar status,i; CSN=0; status=SPI_RW(reg); for(i=0;i void TX_mode(uchar *tx_buf) { CE=0; SPI_write_pload(WRITE_REG+TX_ADDR,TX_ADDRESS,TX_ADR_WIDTH); SPI_write_pload(WRITE_REG+RX_ADDR_P0,TX_ADDRESS,TX_ADR_WIDTH); SPI_write_pload(WR_TX_PLOAD,tx_buf,TX_PLOAD_WIDTH); SPI_RW_reg(WRITE_REG+EN_AA,0X01); SPI_RW_reg(WRITE_REG+EN_RXADDR,0X01);