发布时间 : 星期一 文章2014-2015数字逻辑试卷更新完毕开始阅读
数字电路与逻辑设计期末考试样题
一 二 三 四 五 六 七 八 九 十 合计 一、 TO FILL YOUR ANSWERS IN THE “( )” （1’ X 5）
1. An unused CMOS NAND gate input should be tied to logic ( ) or another input. 2. DAC can proportionally convert ( ) input to analog signal output.
3. A truth table for a ( ) input, 4-output combinational logic function could be stored in a 512?4 EPROM.
4. The RCO output of 74X163 is asserted if and only if the enable signal ( )is asserted and the counter is in state ?1111?.
5. If the signed-magnitude representation is（001101）2 for one number, then it?s 8-bit two?s complement representation is（ ）2.
二、Single selection problems: there is only one correct answer in the following questions.（2’ X 5）
1、An 8-output demultiplexer has ( ) select inputs.
A. 2 B. 3 C. 4 D. 5
2、For a logical function ,which representation as follows is one and only（唯一）. ( )
A. logic expression B. logic diagram C. truth table D. timing diagram
3、In general, to complete the same function, compared to a MOORE machine, the MEALY machine has （ ）。
A. more states B. fewer states C. more flip-flops D. fewer flip-flops
4、To design a “1000001” serial sequence generator by shift registers, at least needs a ( ) bit shift register.
A. 2 B. 3 C. 4 D.5
5、The following logic expressions is equal, and the hazard-free one is ( ).
A. F=B?C?+AC+A?B B. F=A?C?+BC+AB?
C. F=A?C?+BC+AB?+A?B D. F=B?C?+AC+A?B+BC+AB?+A?C?
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三. Combinational Circuit Analysis: [10]
1．Find the minimal product-of-sums expression for F?AB?A'BC'?BC. [4]
2．Write the minterm list expression for F=W+XZ+XY. [3]
F=Σ
WXYZ( )
3．Complete the timing diagram of the circuit below. (Assume that the propagation delay of each gate is one Δ) [3]
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四.Show how to build the following logic function using one 74X138 3-8 binary decoder and some NAND gates.
F = A?BD? + A?CD? + BCD?
Write the truth table and draw the logic diagram. The logic symbol of 74X138 3-to-8 decoder is shown as follows.[10]
五. A 2-bit comparator circuit receives two 2-bit numbers, P (P=P1P0) and Q (Q=Q1Q0). Design a circuit that the
output FP>Q is 1 if and only if P>Q. Please write the truth table for the circuit. [5]
Truth table （真值表） FP>Q
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六. Clocked Synchronous State Machine Design [ 20 total ]
1. Design a clocked synchronous state machine with the state/output table shown below, using D flip-flops. Use two state variables,Q1 Q2, with the state assignment shown as follows. Write transition/output table and excitation/output table. [7]
state/output table： state assignment： transition/output table excitation/output table
2. An excitation/output table of a clocked synchronous state machine using D flip-flops is shown as follows. Write the excitation equations and output equation. [8]
excitation/output table X Q1Q2 0 1 0 0 0 1 /0 0 1 /0 0 1 0 1 /0 1 1 /0 1 0 1 1 /0 0 0 /1
1 1 0 0 /1 1 0 /0 D1D2 / Z
3. The excitation equations and output equitation of a clocked synchronous state machine is shown as follows. Draw the logic diagram using positive-edge-triggered（上升沿触发） J-K flip-flops . [5]
excitation equations： J0=( A⊕Q1 )’ ; K0=( A Q1)’
J1= A⊕Q0 ; K1=(A’Q0)’
output equitation: Y=((AQ1)’(A’Q0))’
S A B C D
X 0 1 B，0 D，1 C，0 A，0 D，0 B，0 A，1 C，0 S*，Z
S Q1 Q2 A 0 0 B 0 1 C 1 0 D 1 1
X 0 1 X 0 1
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