发布时间 : 2024/6/27 1:18:23 星期四 文章基于FPGA的温度监控系统 - 图文更新完毕开始阅读

山东科技大学学士学位论文 附录

reg[4:0] cnt_1m; parameter div_1k = 15'd25000 -1, div_1m = 5'd25 -1;

always @(posedge clk) begin if(~rst) begin cnt_1k <= 0; clk_1k <= 0; end else begin cnt_1k <= cnt_1k + 1; if(cnt_1k == div_1k) begin cnt_1k <= 0; clk_1k <= ~clk_1k; end end end

always @(posedge clk) begin if(~rst) begin cnt_1m <= 0; clk_1m <= 0; end else begin cnt_1m <= cnt_1m + 1; if(cnt_1m == div_1m) begin cnt_1m <= 0; clk_1m <= ~clk_1m; end end end

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山东科技大学学士学位论文 附录

endmodule

2进制转BCD码 module bin2bcd( input [15:0] data, output reg[11:0] bcd_out ); reg[3:0] i; reg[6:0] data_temp; reg[11:0] bcd;

always @(data) begin data_temp[6:0] = data[10:4]; bcd = 0; for(i=0;i<6;i=i+1) begin bcd = {bcd[10:0],data_temp[6]}; if(bcd[3:0] > 4'd4) bcd[3:0] = bcd[3:0] + 4'd3; if(bcd[7:4] > 4'd4) bcd[7:4] = bcd[7:4] + 4'd3; if(bcd[11:8] > 4'd4) bcd[11:8] = bcd[11:8] + 4'd3; data_temp = data_temp << 1; end bcd_out = {bcd[10:0],data_temp[6]}; end

endmodule 显示模块： module disp( input rst, input clk, input [11:0] data, output reg[7:0] seg, output reg[1:0] en

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