发布时间 : 星期六 文章基于LCD1602的简易秒表的设计与实现更新完毕开始阅读
SIGNAL YIMA_DATA_1: std_logic_vector(7 downto 0); --译码数据信号1，秒表百分秒位
SIGNAL YIMA_DATA_2: std_logic_vector(7 downto 0); --译码数据信号2，秒表十分秒位
SIGNAL YIMA_DATA_3: std_logic_vector(7 downto 0); --译码数据信号3，秒表秒钟部分个位
SIGNAL YIMA_DATA_4: std_logic_vector(7 downto 0); --译码数据信号4，秒表秒钟部分十位
SIGNAL YIMA_DATA_5: std_logic_vector(7 downto 0); --译码数据信号5，秒表分钟部分个位
SIGNAL YIMA_DATA_6: std_logic_vector(7 downto 0); --译码数据信号6，秒表分钟部分十位
SIGNAL YIMA_DATA_7: std_logic_vector(7 downto 0); --译码数据信号7，秒表小时部分个位
SIGNAL YIMA_DATA_8: std_logic_vector(7 downto 0); --译码数据信号8，秒表小时部分十位
BEGIN
u1:fpqPORT MAP(clk=>clk1,clkout=>clk2);
u2:cnt10PORT MAP(reset=>en_2,clk=>clk2,en=>en_1,carry=>carry1,q=>q1); u3:cnt10 PORT MAP(reset=>en_2,clk=>carry1,en=>en_1,carry=>carry2,q=>q2); u4:cnt10PORT MAP(reset=>en_2,clk=>carry2,en=>en_1,carry=>carry3,q=>q3); u5:cnt6PORT MAP(reset=>en_2,clk=>carry3,en=>en_1,carry=>carry4,q=>q4); u6:cnt10PORT MAP(reset=>en_2,clk=>carry4,en=>en_1,carry=>carry5,q=>q5); u7:cnt6PORT MAP(reset=>en_2,clk=>carry5,en=>en_1,carry=>carry6,q=>q6); u8:cnt24
PORTMAP(Reset=>en_2,clk=>carry6,en=>en_1,qa=>qa1,qb=>qb1,carry=>carry7);
u9:yimaPORT MAP(data=>q1,dataout=>YIMA_DATA_1,carry=>(carry7 and carry6)); u10:yimaPORT MAP(data=>q2,dataout=>YIMA_DATA_2,carry=>(carry7 and carry6)); u11:yimaPORT MAP(data=>q3,dataout=>YIMA_DATA_3,carry=>(carry7 and carry6)); u12:yimaPORT MAP(data=>q4,dataout=>YIMA_DATA_4,carry=>(carry7 and carry6)); u13:yimaPORT MAP(data=>q5,dataout=>YIMA_DATA_5,carry=>(carry7 and carry6)); u14:yimaPORT MAP(data=>q6,dataout=>YIMA_DATA_6,carry=>(carry7 and carry6)); u15:yimaPORT MAP(data=>qa1,dataout=>YIMA_DATA_7,carry=>(carry7 and carry6)); u16:yimaPORT MAP(data=>qb1,dataout=>YIMA_DATA_8,carry=>(carry7 and carry6)); u17:LCD1602 PORT MAP(YIMA_DATA1=>YIMA_DATA_1,
YIMA_DATA2=>YIMA_DATA_2, YIMA_DATA3=>YIMA_DATA_3, YIMA_DATA4=>YIMA_DATA_4, YIMA_DATA5=>YIMA_DATA_5, YIMA_DATA6=>YIMA_DATA_6, YIMA_DATA7=>YIMA_DATA_7,
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YIMA_DATA8=>YIMA_DATA_8, LCD_Clk=>clk3,
--注意LCD显示的时钟频率和计数模块的频率不一样，LCD显示的频率需要快一些 LCD_Data=>LCD_Data1, carry=>(carry7 and carry6), LCD_RS=>LCD_RS1, LCD_RW=>LCD_RW1, LCD_EN=>LCD_EN1);
u18:fpq1 PORT MAP(clk=>clk1,clkout=>clk3); u19:xiaodouPORT MAP(clk=>clk2,key_en=>start,en_out=>en_1); u20:fuweixiaodouPORT MAP(clk=>clk2,fuwei=>reset1,fuwei_out=>en_2);
END struc;
②500000分频模块fpq
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity fpq is port (
clk : in std_logic; --系统时钟
clkout : out std_logic --系统时钟500000分频后的时钟 ); end fpq;
architecture struc of fpq is signal clktmp : std_logic;
signal tmp : integer range 0 to 249999; --500000分频 begin
process (clk) begin
if clk'event and clk='1' then
if tmp=249999 then
tmp<=0; clktmp<=not clktmp; else
tmp<=tmp+1; end if;
end if;
end process; clkout<=clktmp;
end struc;
③50000分频模块fpq1
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library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity fpq1 is port
( );
end fpq1;
architecture struc of fpq1 is signal clktmp : std_logic;
signal tmp : integer range 0 to 24999; --50000分频 begin
process (clk) begin
if clk'event and clk='1' then
if tmp=24999 then
tmp<=0; clktmp<=not clktmp; else
tmp<=tmp+1; end if;
clk : in std_logic; --系统时钟
clkout : out std_logic --系统时钟50000分频后的时钟
end if; end process; clkout<=clktmp;
end struc;
④10进制计数器模块cnt10
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt10 IS PORT
(reset,en,clk:IN STD_LOGIC;--复位、使能、时钟信号
carry:OUT STD_LOGIC;--进位信号 q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));--输出信号
END CNT10;
ARCHITECTURE rtl OF cnt10 IS
SIGNAL qs :STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL ca :STD_LOGIC;
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BEGIN
PROCESS(clk,reset,en)
BEGIN
IF(reset='1')THEN--采用异步复位 qs<=\ELSIF(clk'EVENT AND clk='1')THEN IF(en='0') THEN
IF(qs=\计数到9
qs<= \下一状态为0 ca<='1';--进位信号变为‘1’ ELSE qs<= qs+1;--qs自增
ca<='0';--进位信号保持在‘0’ END IF; END IF; END IF; END PROCESS;
PROCESS(ca) BEGIN q<=qs; carry<=ca; END PROCESS; END rtl;
⑤6进制计数器模块cnt6
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt6 IS
PORT
(reset,en,clk:IN STD_LOGIC;--复位、使能、时钟信号
carry :OUT STD_LOGIC;--进位信号
q :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));--输出信号
END CNT6;
ARCHITECTURE rtl OF cnt6 IS
SIGNAL qs :STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL ca :STD_LOGIC;
BEGIN
PROCESS(clk)
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