发布时间 : 星期三 文章数电实验 - 图文更新完毕开始阅读
juzhenxianshi:process(clk) begin
if(clk='1' and clk'event)then --逐行扫描显示图形
if saomiao(7 downto 0)=\or saomiao(7 downto 0)=\then saomiao(7 downto 0)<=\;g_data<= g_matrix0;r_data<= r_matrix0; elsif saomiao(7 downto 0)=\then
saomiao(7 downto 0)<=\;g_data<= g_matrix1;r_data<= r_matrix1; elsif saomiao(7 downto 0)=\then
saomiao(7 downto 0)<=\;g_data<= g_matrix2;r_data<= r_matrix2; elsif saomiao(7 downto 0)=\then
saomiao(7 downto 0)<=\;g_data<= g_matrix3;r_data<= r_matrix3; elsif saomiao(7 downto 0)=\then
saomiao(7 downto 0)<=\;g_data<= g_matrix4;r_data<= r_matrix4; elsif saomiao(7 downto 0)=\then
saomiao(7 downto 0)<=\;g_data<= g_matrix5;r_data<= r_matrix5; elsif saomiao(7 downto 0)=\then
saomiao(7 downto 0)<=\;g_data<= g_matrix6;r_data<= r_matrix6; elsif saomiao(7 downto 0)=\then
saomiao(7 downto 0)<=\;g_data<= g_matrix7;r_data<= r_matrix7; end if; end if;
end process juzhenxianshi; end a;
2.分频模块
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity div is
Port ( clkin:in STD_LOGIC; clkout_kb:out STD_LOGIC; clkout_dianzhen:out STD_LOGIC; clkout_controller:out STD_LOGIC; clkout_static:out STD_LOGIC
); end div;
architecture one of div is
signal clk1:std_logic:='0';----keyboard fenpin
signal counter1:integer range 0 to 16666; --分频计数信号 signal clk2:std_logic:='0';----dianzhen fenpin signal counter2:integer range 0 to 49999;--500HZ分频
signal clk3:std_logic:='0';----controller
signal counter3:integer range 0 to 2499999;--2499999 10HZ分频 1666666 15HZ分频
signal clk4:std_logic:='0';----static
signal counter4:integer range 0 to 24999;--2499999 10HZ分频 1666666 15HZ分频 begin
process(clkin)---kb begin
if clkin'event and clkin='1'then if counter1=16666 then clk1<=not clk1; counter1<=0; else
counter1<=counter1+1; --加计数 end if; end if; end process;
process(clkin)---dianzhen begin
if clkin'event and clkin='1'then if counter2=49999 then clk2<=not clk2; counter2<=0; else
counter2<=counter2+1; end if;
end if; end process;
process(clkin)---controller begin
if clkin'event and clkin='1'then if counter3=2499999 then clk3<=not clk3; counter3<=0; else
counter3<=counter3+1; end if; end if; end process;
process(clkin)---static begin
if clkin'event and clkin='1'then if counter4=24999 then clk4<=not clk4; counter4<=0; else
counter4<=counter4+1; end if; end if; end process;
clkout_kb<=clk1;
clkout_dianzhen<=clk2; clkout_controller<=clk3;
clkout_static<=clk4; 将分得的时钟信号分别赋给不同模块 end one;
3.数码管显示模块
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_Unsigned.all;
use ieee.std_logic_ARITH.all;
entity static is port(
clear,clk_in:in std_logic;
num:out std_logic_vector( 6 downto 0); --七段数码管控制型号 cat:out std_logic_vector(5 downto 0); --数码管选通信号 to_display:in std_logic_vector(41 downto 0) —-数据信号 ); end entity;
architecture one of static is
signal status:integer range 0 to 6; begin
process(clk_in) begin
if(clk_in'event and clk_in='1') then if status=6 then status<=1;
else status<=status+1; --加计数实现状态切换依次扫描数码管 end if; end if; end process;
process(status) begin
case status is
when 1=> num<=to_display(41 downto 35);cat<=\; when 2=> num<=to_display(34 downto 28);cat<=\; when 3=> num<=to_display(27 downto 21);cat<=\; when 4=> num<=to_display(20 downto 14);cat<=\; when 5=> num<=to_display(13 downto 7);cat<= \;
when 6=> num<=to_display(6 downto 0);cat<= \; --根据数据控制数码管选通
when others => num<=\;cat<=\; end case; end process; end one;