发布时间 : 星期二 文章数电实验 - 图文更新完毕开始阅读
g_matrix6:out std_logic_vector(7 downto 0); g_matrix7:out std_logic_vector(7 downto 0);
r_matrix0:out std_logic_vector(7 downto 0); r_matrix1:out std_logic_vector(7 downto 0); r_matrix2:out std_logic_vector(7 downto 0); r_matrix3:out std_logic_vector(7 downto 0); r_matrix4:out std_logic_vector(7 downto 0); r_matrix5:out std_logic_vector(7 downto 0); r_matrix6:out std_logic_vector(7 downto 0); r_matrix7:out std_logic_vector(7 downto 0); to_display:out std_logic_vector(41 downto 0);
message1: in std_logic_vector(7 downto 0) );
End component; --前半部分主要是定义各按键
Component div --分频 Port ( clkin:in STD_LOGIC; clkout_kb:out STD_LOGIC; clkout_dianzhen:out STD_LOGIC; clkout_controller:out STD_LOGIC; clkout_static:out STD_LOGIC );
End component;
Component static --数码管 port(
clear,clk_in:in std_logic;
num:out std_logic_vector( 6 downto 0); cat:out std_logic_vector(5 downto 0); to_display:in std_logic_vector(41 downto 0) );
End component;
type matrix_type IS array (7 downto 0) of std_logic_vector (7 downto 0); signal g_matrix : matrix_type; -----matrix 是二维8*8数组，信号 signal r_matrix : matrix_type; -----matrix 是二维8*8数组，信号 signal message2: std_logic_vector(7 downto 0); signal kb_clk: std_logic; signal dianzhen_clk: std_logic; signal controller_clk: std_logic; signal static_clk: std_logic;
signal display:std_logic_vector(41 downto 0); Begin
U1: dianzhenxianshi port map( --点阵显示 clk=>dianzhen_clk, reset=>reset1,
g_matrix0=>g_matrix(0),g_matrix1=>g_matrix(1),g_matrix2=>g_matrix(2), g_matrix3=>g_matrix(3),g_matrix4=>g_matrix(4),g_matrix5=>g_matrix(5), g_matrix6=>g_matrix(6),g_matrix7=>g_matrix(7),
r_matrix0=>r_matrix(0),r_matrix1=>r_matrix(1),r_matrix2=>r_matrix(2), r_matrix3=>r_matrix(3),r_matrix4=>r_matrix(4),r_matrix5=>r_matrix(5), r_matrix6=>r_matrix(6),r_matrix7=>r_matrix(7),
hang=>hang1,g_com=>g_com1,r_com=>r_com1 --传入行列信号
);
U2: controller port map( --控制模块 clk=>controller_clk ,reset=>reset1,
g_matrix0=>g_matrix(0),g_matrix1=>g_matrix(1),g_matrix2=>g_matrix(2), g_matrix3=>g_matrix(3),g_matrix4=>g_matrix(4),g_matrix5=>g_matrix(5), g_matrix6=>g_matrix(6),g_matrix7=>g_matrix(7),
r_matrix0=>r_matrix(0),r_matrix1=>r_matrix(1),r_matrix2=>r_matrix(2), r_matrix3=>r_matrix(3),r_matrix4=>r_matrix(4),r_matrix5=>r_matrix(5), r_matrix6=>r_matrix(6),r_matrix7=>r_matrix(7), --存入向量表中 to_display=>display, message1=>keyin1 );
U4: div port map(
clkin=>clk1,clkout_kb=>kb_clk, clkout_dianzhen=>dianzhen_clk, clkout_controller=>controller_clk, clkout_static=>static_clk);
U5: static port map(clear=>reset1,clk_in=>static_clk, num=>num1,cat=>cat1,to_display=>display); END architecture one;
分模块说明： 1、点阵显示模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_Unsigned.all; use ieee.std_logic_ARITH.all; ENTITY dianzhenxianshi is port(
clk:in std_logic; reset:in std_logic;
g_matrix0:in std_logic_vector(7 downto 0);
g_matrix1:in std_logic_vector(7 downto 0); --绿色扫描向量 g_matrix2:in std_logic_vector(7 downto 0); g_matrix3:in std_logic_vector(7 downto 0); g_matrix4:in std_logic_vector(7 downto 0); g_matrix5:in std_logic_vector(7 downto 0); g_matrix6:in std_logic_vector(7 downto 0); g_matrix7:in std_logic_vector(7 downto 0);
r_matrix0:in std_logic_vector(7 downto 0);
r_matrix1:in std_logic_vector(7 downto 0); --绿色扫描向量 r_matrix2:in std_logic_vector(7 downto 0); r_matrix3:in std_logic_vector(7 downto 0); r_matrix4:in std_logic_vector(7 downto 0); r_matrix5:in std_logic_vector(7 downto 0); r_matrix6:in std_logic_vector(7 downto 0); r_matrix7:in std_logic_vector(7 downto 0);
hang: out std_logic_vector(7 downto 0); g_com: out std_logic_vector(7 downto 0); r_com: out std_logic_vector(7 downto 0));
End dianzhenxianshi;
architecture a of dianzhenxianshi is
signal saomiao:std_logic_vector(7 downto 0); --扫描信号 signal g_data:std_logic_vector(7 downto 0); signal r_data:std_logic_vector(7 downto 0); Begin
g_com<=g_data;r_com<=r_data; hang<=saomiao;