发布时间 : 星期三 文章FPGA实验报告 - 图文更新完毕开始阅读
图3.33 使用KH-33001/2/3 下载板时的跳线
图3.34
若使用KH-33004/5 下载板则只需要将数码管的短路夹跳至JP2 即可，如图3.33 所示 图3.34 使用KH-33004/5 下载板时的跳线
八、实验程序
1. VHDL 程序 library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity traffic is
Port (Clock,Reset:in std_logic;
Strait_A_Out,Block_A_Out,Turn_A_Out,Strait_B_Out,Block_B_Out,Turn_B_Out:out std_logic;
Count_Down_LCD:out std_logic_vector(6 downto 0); Road_sign: out std_logic_vector(13 downto 0); Ctr:out std_logic ); end entity;
architecture traffic of traffic is signal Clock_4Hz,LCD:std_logic;
signal Count_4Hz:std_logic_vector(4 downto 0); signal Count_1Hz:std_logic_vector(1 downto 0); signal Clock_1Hz:std_logic;
signal Count_Down:std_logic_vector(2 downto 0);
--signal Count_Down_LCD:std_logic_vector(6 downto 0); signal q:std_logic_vector(13 downto 0); signal State:std_logic_vector(1 downto 0); signal Count:std_logic_vector(2 downto 0);
signal Strait_A,Block_A,Turn_A,Strait_B,Block_B,Turn_B,Blink:std_logic; --//wire [13:0] Road_sign
constant Strait_Block :std_logic_vector:=\constant Block_Turn :std_logic_vector:=\constant Turn_Block :std_logic_vector:=\constant Block_Strait :std_logic_vector:=\
begin
Ctr<='1';
Strait_A_Out<=Strait_A and (Clock_4Hz or Blink); Strait_B_Out<=Strait_B and (Clock_4Hz or Blink); Block_A_Out<=Block_A and (Clock_4Hz or Blink); Block_B_Out<=Block_B and (Clock_4Hz or Blink); Turn_A_Out<=Turn_A and (Clock_4Hz or Blink); Turn_B_Out<=Turn_B and (Clock_4Hz or Blink);
Road_sign(13 downto 7) <= q(13 downto 7);
Road_sign(6 downto 0) <= ((not q(6))and (Clock_4Hz or Blink))&((not q(5))and (Clock_4Hz or Blink))&((not q(4))and (Clock_4Hz or Blink))& ((not q(3))and (Clock_4Hz or Blink))&((not q(2))and (Clock_4Hz or Blink))&((not q(1))and (Clock_4Hz or Blink))&
((not q(0))and (Clock_4Hz or Blink));
--//************* Generate 4Hz Clock Signal from 1kHz Clock Signal ********** process(Clock) begin
if Clock'event and Clock='1' then Count_4Hz <= Count_4Hz-1; if Count_4Hz=\
Clock_4Hz <= not Clock_4Hz;--Generate 4Hz clock signal end if; end if;
end process;
--//************* Generate 1Hz Clock Signal from 4Hz Clock Signal ***********
process (Clock_4Hz) begin
if Clock_4Hz'event and Clock_4Hz='1' then Count_1Hz <= Count_1Hz-1; if Count_1Hz=\
Clock_1Hz <= not Clock_1Hz; --//Generate 1Hz clock signal end if; end if;
end process;
--//**************************** Main Program ******************************* process (Clock_1Hz) begin
if Clock_1Hz'event and Clock_1Hz='1' then if Reset='1' then
State<=Strait_Block; Count_Down<=\
Strait_A<='1'; Block_A<='1'; Turn_A<='1'; Strait_B<='1'; Block_B<='1'; Turn_B<='1'; Count_Down_LCD<=\ Blink<='1';
else
Count_Down<=Count_Down-1; if State=Strait_Block then
Strait_A<='1'; Block_A<='0'; Turn_A<='0'; Strait_B<='0'; Block_B<='1'; Turn_B<='0'; if Count_Down=\ State<=Block_Turn; end if;
elsif State=Block_Turn then
Strait_A<='0'; Block_A<='1'; Turn_A<='0'; Strait_B<='0'; Block_B<='0'; Turn_B<='1'; if Count_Down=\ State<=Turn_Block; end if;
elsif State=Turn_Block then
Strait_A<='0'; Block_A<='0'; Turn_A<='1'; Strait_B<='0'; Block_B<='1'; Turn_B<='0'; if Count_Down=\ State<=Block_Strait; end if;
elsif State=Block_Strait then
Strait_A<='0'; Block_A<='1'; Turn_A<='0'; Strait_B<='1'; Block_B<='0'; Turn_B<='0'; if Count_Down=\ State<=Strait_Block; end if; end if;
case Count_Down is
when \//1 when \//2 when \ when \//4 when \ when \//6 when \ when \ end case ;
if Count_Down>=3 then Blink<='1'; else
Blink<='0'; end if; end if;